slew rate control

[richardb]

I'm using an18f47q43 for some software spi comms and the slew rate looks a bit slow compared to other pics at approx. 200ns, I noticed the datasheet has mention of slew rate control so I tried adding the following after setalldigital

SLRCONA = 0
SLRCONB = 0
SLRCONC = 0
SLRCOND = 0
SLRCONE = 0
and also tried setting them all to 255 but it doesn't seem to make any difference if they are enabled or disabled.

am I supposed to do this in a specific way?

Rich

[Jerry Messina]

Setting them to 0 should work, but SetAllDigital should already be doing that for you.

The library file SetDigitalIO.bas, version v3.0 has an #option that controls this, and it defaults to setting the slew-rate back to normal for all the ports

Code: Select all

#option DIGITALIO_SLEWRATE = 0      // 0=normal, 1=slow (SLRCON default)

For an 18F47Q43, SetAllDigital should produce:

Code: Select all

?I000000_F000_000018_M000000 ; L#MK setalldigital
    MOVLB 4
    CLRF ANSELA,1
    CLRF ANSELB,1
    CLRF ANSELC,1
    CLRF ANSELD,1
    CLRF ANSELE,1
    MOVLB 0
    CLRF CM1CON0,1
    CLRF CM2CON0,1
    MOVLB 4
    CLRF SLRCONA,1
    CLRF SLRCONB,1
    CLRF SLRCONC,1
    CLRF SLRCOND,1
    CLRF SLRCONE,1

[richardb]

Sorry for the slow reply,

Ok, this is a bit embarrassing.

In my defence this was an old board design where I have just changed to a new processor, and a new fault had been introduced.

I had 1k series resistors inline with the fpga as level shifters as the fpga has clamp diodes. but this value is really too high.
I noticed the slew-rate was slow but couldn't see in the datasheet what was "normal" for high and low slew rates. and changing from high to low didn't make a difference as it was hidden by the resistor/probe rc time constant.


measuring now before the resistor the risetime is ~20ns on slow and probably below 3ns on fast.

Thanks again Jerry for the quick reply

[Jerry Messina]

Glad you got it sorted out.

They do show some typical values for the IO slew rate in the datasheet (table 47-10). What you're seeing seems to pretty much match...

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