Generating phase-angle control signals

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Generating phase-angle control signals

Post by SHughes_Fusion » Mon Aug 17, 2015 7:43 am

I'm developing a system which phase-angle controls the input to a transformer and was wondering if I could take advantage of the various PIC peripherals to take some (or all!) of the load off the processor in doing this.

Basically, I have a pulse input from a zero-cross detector and need to generate a short pulse a variable time later to turn a triac on.

I was planning to use the Compare module to generate the delay with a interrupt triggered by the zero-cross pulse starting the compare process.

I was wondering if I could somehow take advantage of the SR Latch to generate the pulse but I can't work out how to get the two modules to work together. The datasheet suggests the SR Latch can be used as a one-shot but I can't work out how to achieve this with a repeatable pulse length - it strikes me that the reset pulses just come at fixed intervals so depending when you trigger it you could get any length of pulse as a result. Or am I misunderstanding how this works?

Can anyone suggest anything to look at, or any other way in which I may be able to do this? I'm using the 18F26K22.

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Re: Generating phase-angle control signals

Post by Jerry Messina » Mon Aug 17, 2015 2:40 pm

I'm like you. I'm not sure I see how you could sync to the DIVSRCLK to know what it's going to do. The SR Latch looks to be the guts of a 555 timer IC. The only applications I've seen it used on are Capactive touch where they hookup an RC network to feedback into the comparators as an oscillator.

You might be able to use the SR latch in a different way. How about this:

You want to produce two time periods, T1 and T2 triggered by the output of the ZCD.
T1 is the time from the ZCD to when the output pulse starts, and T2 is the output pulse width.

Use TMR1 + CCP1 Compare to produce T1, and TMR3 + CCP3 Compare to produce T2.
The SR Latch will be used to produce the final output pulse on the SRQ pin. The SR latch can get its S and R inputs via internal connection from the output of the two comparators C1OUT and C2OUT, so use comparator C1IN+ as the "S input pin", and comparator C2IN+ as the "R input pin".

Connect as follows:
- ZCD output to TMR1 Gate input (T1G).
- CCP1 compare output to comparator C1IN+ (C1OUT->SR Latch Set input) and also to the TMR3 Gate input (T3G)
- CCP3 compare output to comparator C2IN+ (C2OUT->SR Latch Reset input)
- SR Latch SRQ is the final output signal.

The ZCD output goes high enabling the T1GATE, so CCP1 starts couting time period T1 (delay from ZCD to output pulse high).
On CCP1 match at the end of T1, CCP1 output pin goes high, the SR Latch Set input goes high, and that sets the SRQ output high also. This is the start of the output pulse.

Since CCP1 output is also connected to T3GATE, CCP3 now starts to count. This starts time period T2.
On CCP3 match at the end of T2, CCP3 output pin goes high, the SR Latch Reset input goes high (Reset dominates), and the SRQ output goes low.

Detect the CCP3IF and reset everybody to start over. You might be able to use the CCP Special Event Trigger to reset things too, but I haven't thought that through.

Uses a lot of modules, but if you could get the Special Event Trigger to work the whole thing might be able to run without any interaction.

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