Shifting In 40 Bits at 10 MHz

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Jon Chandler
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Shifting In 40 Bits at 10 MHz

Post by Jon Chandler » Mon Aug 14, 2017 5:06 pm

A simple project I agreed to do has turned more complicated. I need to read 40 bits clocked out at 10 MHz.

I'm using a PIC18F25k22 with a 16 MHz crystal and 4xPLL enabled for a clock speed of 64 MHz.

My first thought was to use shift.bas. Is there any chance this will work at 10 MHz? If it does work, it will need modification as it's currently limited to 32 bits.

I think the practical alternative is a string of TTL serial/parallel shift registers, and reading the 40 bits with MCP23017 I2C port expanders.

There are a great number of unknowns about this project at this point, such as how often this signal is even sent. I hope to get some logic analyzer output of what's actually going on vs. what we guess is going on; just trying to figure out possible options at this point.

Thanks,

Jon

Jerry Messina
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Re: Shifting In 40 Bits at 10 MHz

Post by Jerry Messina » Mon Aug 14, 2017 11:14 pm

Is there any chance this will work at 10 MHz?
Nope.

So you have a stream of 40 bits. What other signals are there other than the data? A clock? Any sort of sync signal?

It might be possible to use the USART in synchronous slave mode to receive the bit stream assuming you have a clock signal. In sync mode there's no start or stop bits (just the eight data bits) so you'd have 5 bytes to deal with, and only a 2 byte buffer. That means you'd have to read bytes out of the USART rx fifo within 2x800ns time. It might be doable, if the USART will even clock in data that fast.

I'd say try the SPI in slave mode but there you only have a single input register so there's no way you'd ever be able to keep up with it.

I think you need a little more info on how the serial stream works. You especially need to know what marks the start of a 40-bit message and if there's any gap between the bits or it's just a constant stream @ 10MHz.

Jon Chandler
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Re: Shifting In 40 Bits at 10 MHz

Post by Jon Chandler » Tue Aug 15, 2017 12:55 am

Sorry, I left out a few details that I know.

There is a clock signal synchronized with the data stream. I don't know if the clock signal is continuous or available only when data is available.

There is also an enable signal that allows the system to clock out the 40 data bits
This should function as a sync/start signal.

Still a challenge I think!
Jon

Check out the TAP-28 PIC Application board at http://www.clever4hire.com/throwawaypic/

Jerry Messina
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Re: Shifting In 40 Bits at 10 MHz

Post by Jerry Messina » Tue Aug 15, 2017 10:19 am

If the clock is continuous then you'll likely need some sort of gating logic between the clock and the enable signal.

You need the timing details between the clock, data, and the enable. Once you have that then we can figure out what to do with it.

You might be stuck using some external shift registers, but I wouldn't give up hope quite yet.

Jon Chandler
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Re: Shifting In 40 Bits at 10 MHz

Post by Jon Chandler » Tue Aug 15, 2017 12:32 pm

Thanks Jerry. I'll post more when I have solid info.

Jon
Jon

Check out the TAP-28 PIC Application board at http://www.clever4hire.com/throwawaypic/

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