Doj wrote:If this old news impresses you wait till you hear about the new 16F Core!!!
It's not that impressive. Just wanted to post in case someone has heard about any details.
As for the 16F serie, I think it's an UGLY architecture, and it will remain ugly!
We cannot enhance an ugly core (my personal opinion of course).
For me, the 18F serie is one of the best series especially for to be used with high level language.
The enhancements to the 16F series will never make it at the same quality of the 18F serie, and the 18F serie now costs about the same as the 16F serie. Personally I'll never go for a 16F for a commercial product unless I cannot find any equivalent in 18F version (12bit core or 14bit low pin devices).
With the enhancement to the 16F serie, Microchip tries to move the 16F serie to the same level as 18F serie. Really a continious fiddling (a lot of limitations will still exists like as banking).
To see and compare them to a clean architecture, try to see the ARM-CORTEX based serie of microcontrollers made by Luminary. They costs less than 1 $US per unit, have a higher speed (50 MHz is a std), and have a lot more peripherals, with a 32 Bit core, and a very clean architecture (No banking, fully flat memory model, very clean assembler, software stack, vectored interrupts, ....)!!!
For users who would be interrested, for reference, here is the new enhancement that we "probably" would have in the new 16F enhanced core (from an unofficial source - Microchip did not communicated about that, just two guys from Micrcohip gave some info on mailing lists)
1) Increase the maximum program memory: can address up to 32K (vs 8K of PIC16)
2) Increase the maximum data memory
3) Increase of hardware stack level to 16.
4) Reduce the penalty for paging/banking
- by introducing new BSR register. Hence the old PR0/PR1 is no more exist.
- by introducing new MOVLP instruction.
5) Automatic ISR context saving for W, STATUS, BSR, FSR0, FSR1, PCLATH.
6) Has 2 indirect RAM accesses through INDF0 and INDF1. Support pre/post increment/decrement.
7) Relative branch (signed and unsigned offset).
Stack over/underflow cause Reset.
9) Stack can be accessed via SPTR and TOS.
10) RESET instruction.
11) Some advanced arithmetic instruction - some already exist in PIC18, some are NOT.
12) Enhanced program memory read. Device ID, user ID and configuration word are now readable by the firmware.
The only good news I can personally see from these enhancement is that we could have (maybe easily) a port of Swordfish Basic for this serie of 16F core
Regards
octal