I have been having an issue with noise on a board that has a a pic18f47q43 in a socket its running with internal oscilator at 64MHz,
i originally had the config as below.
Code: Select all
Config
FEXTOSC = OFF, // Oscillator not enabled
RSTOSC = HFINTOSC_64MHZ,// HFINTOSC with HFFRQ = 64 MHz and CDIV = 1:1
CLKOUTEN = OFF // CLKOUT function is disabled
so i have designed a board that can plug into the old 40 pin socket of the 47q43 using a 57q43 and a seperate 16MHz xtal osc
so i tried running with new board which was ok but had the same problem and have now tried to disconnect the osc to prove that the pic is running from xtal but the pic still runs.
i'm using the confic below from the code generator.
Code: Select all
config
FEXTOSC = HS, // HS (crystal oscillator) above 8 MHz
RSTOSC = EXTOSC_4PLL,// EXTOSC with 4x PLL, with EXTOSC operating per FEXTOSC bits
CLKOUTEN = OFF, // CLKOUT function is disabled
PR1WAY = ON, // PRLOCKED bit can be cleared and set only once
CSWEN = ON, // Writing to NOSC and NDIV is allowed
FCMEN = OFF, // Fail-Safe Clock Monitor disabled
MCLRE = EXTMCLR, // If LVP = 0, MCLR pin is MCLR; If LVP = 1, RE3 pin function is MCLR
PWRTS = PWRT_OFF, // PWRT is disabled
MVECEN = OFF, // Interrupt contoller does not use vector table to prioritze interrupts
IVT1WAY = ON, // IVTLOCKED bit can be cleared and set only once
LPBOREN = OFF, // Low-Power BOR disabled
BOREN = SBORDIS, // Brown-out Reset enabled , SBOREN bit is ignored
BORV = VBOR_1P9, // Brown-out Reset Voltage (VBOR) set to 1.9V
ZCD = OFF, // ZCD module is disabled. ZCD can be enabled by setting the ZCDSEN bit of ZCDCON
PPS1WAY = OFF, // PPSLOCKED bit can be set and cleared repeatedly (subject to the unlock sequence)
STVREN = ON, // Stack full/underflow will cause Reset
LVP = ON, // Low voltage programming enabled. MCLR/VPP pin function is MCLR. MCLRE configuration bit is ignored
XINST = OFF, // Extended Instruction Set and Indexed Addressing Mode disabled
WDTCPS = WDTCPS_31, // Divider ratio 1:65536; software control of WDTPS
WDTE = OFF, // WDT Disabled; SWDTEN is ignored
WDTCWS = WDTCWS_7, // window always open (100%); software control; keyed access not required
WDTCCS = SC, // Software Control
BBSIZE = BBSIZE_512,// Boot Block size is 512 words
BBEN = OFF, // Boot block disabled
SAFEN = OFF, // SAF disabled
DEBUG = OFF, // Background Debugger disabled
WRTB = OFF, // Boot Block not Write protected
WRTC = OFF, // Configuration registers not Write protected
WRTD = OFF, // Data EEPROM not Write protected
WRTSAF = OFF, // SAF not Write Protected
WRTAPP = OFF, // Application Block not write protected
CP = OFF // PFM and Data EEPROM code protection disabled
should the pic run with no external xrystal? with this confic
is there a fallback oscilator that its running from ?
can somone suggest another config or think of a way to prove its running from the internal osc or the external one?
Thanks in advance.
Rich